Exemplary embodiments of the present invention relate to fabrication of a semiconductor device, and more particularly, to a method for fabricating a semiconductor device using a spacer patterning technique.
As the demand for high capacity semiconductor memory devices has continually increased, much attention has been paid to increasing the integration density of these semiconductor memory devices. In order to increase the integration density of semiconductor memory devices, a number of different approaches have been made to form a plurality of memory cells on a single wafer by reducing the chip size and/or changing the cell structure. With regards to methods for increasing integration density by changing the cell structure, attempts have been made to reduce a cell area by changing the planar arrangement of active regions or changing the cell layout. One of these approaches has been to change the layout of the active region from an 8F2 layout to a 6F2 layout. A device having a 6F2 layout may be defined as a semiconductor device having a unit cell which has a bit line length direction of 3F and a word line length direction of 2F, so that its area is 6F2. A DRAM having a 6F2 layout has an active region which is obliquely disposed, and two unit cells that are disposed within one active region. When compared with a DRAM having an 8F2 layout, the DRAM having a 6F2 layout has a higher integration density in that two storage node contact plugs are disposed between bit lines and the storage node contact plugs pass through a bit line contact within the active region. However, although the 6F2 layout reduces the chip size and thus increases the productivity, the adjacent active regions become very close to each other. As the active regions become closer, the optical proximity effect (OPE) can greatly influence the exposure process. Therefore, there is a growing need for performing an optical proximity correction (OPC) in order to form patterns that have the desired shape.
With the need for performing OPC, it becomes more difficult to perform a single exposure process even in an immersion exposure apparatus during a device isolation process of a DRAM having a sub-40 nm 6F2 layout, because a pitch between device isolation regions is less than a pitch of an 8F2 layout. Hence, a spacer patterning technique (SPT) is applied. The spacer patterning technique is performed using a positive method or a negative method. Since the negative method can reduce a mask process by one step, in which it is greatly advantageous in view of the process simplification. However, in the spacer patterning technique according to the negative method, a critical dimension (CD) of a partition directly influences a CD of an active region. Specifically, in a partition forming process applied in a current spacer patterning technique, a partition mask is applied to only a cell mat region where an active region will be formed, and a partition mask is not applied to regions other than the cell mat region, for example, a core region and a peripheral region. Accordingly, patterns are formed in the cell region in the partition forming process, whereas no patterns are formed in the core region and the peripheral region. Patterns are formed in the core region and the peripheral region when a cutting mask is applied.
In this case, the partition CD itself is transferred on the active region in a cell block edge region, which is an edge region of the cell mat region, and directly influences the CD uniformity even when a slight error exists in the OPC process. Therefore, a defect may occur in the CD uniformity, or a defect such as a pattern thinning or bridge may occur. As illustrated in FIG. 1 which shows the cell block edge region formed by a negative method (a) and a positive method (b) in the spacer patterning technique, a bridge defect was found in cell block edge regions A1 and A2.
Referring to FIG. 1, patterns 100 and 110 in the center region of the cell mat are normally formed, whereas adjacent patterns are coupled together in the cell block edge regions A1 and A2 which are edge regions of the cell mat. That is, bridge defects 105 and 115 can occur in the cell block edge regions A1 and A2. Defects such as bridges in the cell block edge regions occur due to a large mask CD difference in each region, an influence of an OPC, or a different open ratio in the partition mask. Since fabrication of the mask includes an exposure process that uses an E-beam, then an optical proximity effect can occur. This can result in causing a different mask CD in the cell block edge region. When the optical proximity effect and the different mask CD become greater in a direction of the cell edge region rather than the cell center region, a local CD uniformity is degraded, and the bridge defects 105 and 115 can occur as illustrated in FIG. 1.
As shown in Table of FIG. 2, when the partition mask is applied to only the cell mat region, the entire wafer CD uniformity in the average cell block edge region (10.89 nm) is about two times larger that of the standard deviation (3σ) of that of the average center region (4.78 nm) in the cell mat region. This is because the mask CD of the cell block edge region changes due to the influence of the optical proximity effect brought about by the exposure process using E-beam in the fabrication of the mask. Due to the change of the mask CD, a local CD uniformity characteristic is degraded in a direction of the cell block edge region. Also, in the partition mask, an opening exists in the cell mat region, but the remaining regions are blocked. Thus, the open ratio is different in each region. Due to the different open ratio in each region, a CD difference is caused by flare noise that can occur during the exposure process. Consequently, a CD uniformity characteristic may be degraded, and as a result bridge defects may arise in the cell edge region.
Furthermore, since the patterns are formed in only the cell mat region in the partition process and no patterns are formed in the remaining regions, a pattern density of the cell mat region is different from a pattern density of the remaining regions. If deposition, etching and planarization processes subsequent to the partition mask are performed so that the pattern densities in the respective regions are different from one another, then the respective regions have different bias values and profiles. Thus the uniformity is influenced which can degrade the CD uniformity of the active region. A resolution enhancement lithography assisted by chemical shrink (RELACS) process is used in a cutting mask on the core region and the peripheral region. Consequently, in the case of a minimum line pattern, since a CD must be set smaller by an RELACS bias, it is difficult to ensure a satisfactory process margin.